registrar@vssut.ac.in +91 8480441756

ବୀର ସୁରେନ୍ଦ୍ର ସାଏ ବୈଷୟିକ ବିଶ୍ୱବିଦ୍ୟାଳୟ

वीर सुरेंद्र साई प्रौद्योगिकी विश्वविद्यालय

Veer Surendra Sai University of Technology

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Dr. Manoranjan Pradhan

Associate Professor

Qualification : B.E–1992 (U.C.E.,Burla) M.E–2005(U.C.E.,Burla) Ph.D (Engineering )–2013 (Sambalpur University)

Specialization : FPGA basedVLSI Design, Microprocessor

9437419566 mpradhan_etc@vssut.ac.in

B.E–1992 (U.C.E.,Burla) M.E–2005(U.C.E.,Burla) Ph.D (Engineering )–2013 (Sambalpur University)

FPGA basedVLSI Design, Microprocessor

Teaching-23 years,Research-16 years

Graduate Level : Microprocessor, Microcontroller and Embedded System
Post Graduate Level : Digital CMOS VLSI Design, High Level VLSI Design.

FPGA based VLSI Design, Vedic algorithm architecture, Redundant Binary architecture

Ph. D. Candidates : Degree Awarded -03, Continuing-03
M. Tech. Candidates : Degree Awarded -26, Continuing-1
DATA TO BE UPDATED...
Life member of ISTE-LM31263
  1. AICTE MODROB Project-Modernization of Microcontroller and Embedded System Lab (8.5 Lakh),2017-19

International Publications

  1. R. Barik ,M.Pradhan,R.Panda.Time Efficient Signed Vedic Multiplier using Redundant Binary Representation,IET The Journal of Engineering,3,pp.60-68,2017, UK.
  2. R.Barik M.Pradhan.ASIC and FPGA Implementation of Cube Architecture,IET Computer & Digital Techniques,11(1),pp.43-49,2016, UK.
  3. R.Barik, M.Pradhan,Area-Time Efficient Square Architecture. Advances in Modeling, AMSE Journal, Series D, Computer Science and Statistics, 20(1),pp.21-34,2015, France. [SCImago journal and country rank value-0.12, H index: 6 ](Accepted)
  4. B.Bhoi,M.Pradhan, A high speed Divider Architecture using Paravartya Sutra of Vedic Mathematics,International Journal of Applied Engineering and Research,10,pp.13365-13375,2015,India. [SCImago journal and country rank value-0.13, H index: 5 ]
  5. M.Pradhan,R.Panda, High speed multiplier using Nikhilam Sutra algorithm of Vedic mathematics,Tayler & Francis,International Journal of Electronics, 101(3),pp. 300-307,2014,UK.[Impact factor: 0.56], [SCImago journal and country rank, subject category: Q2, H index: 38 ]
  6. M.Pradhan,R.Panda,Speed Optimization of Vedic Multiplier, Advances in Modeling,AMSE Journal, Series A, General Mathematics,pp.49,21,2012,France.[SCImago journal and country rank value-0.12, H index: 6 ]
  7. M.Pradhan,R. Panda,Design and Implementation of 16-bit processor.Advances in Modeling,AMSE Journal, Series D, Computer Science and Statistics,17(1),pp.1-14,2012, France.[SCImago journal and country rank value-0.12, H index: 6 ].
  8. S,Sahu,B.Bhoi,M.Pradhan. Improved Redundant Binary Adder Realization in FPGA,Journal of Circuits, Systems and Computers,World Scientific Publishing Company,pp.2150287,June 2021.
  9. M.Pradhan,R. Panda,Design and Implementation of Vedic multiplier. Advances in Modeling,AMSE Journal, Series D, Computer Science and Statistics,15(1),pp.1-19,2010, France.[SCImago journal and country rank value-0.12, H index: 6 ].
  10. S,Sahu,B.Bhoi,M.Pradhan. Fast Signed multiplier using Vedic Nikhilam architecture,IET Circuits, Devices & Systems,14(8),pp1160-1166,Dec 2020.
  11. B.Bhoi,N.Mishra,M.Pradhan.Synthesis and simulation study of non restoring cell architecture layout in perpendicular nano magnetic logic,Journal of Computational Electronics,19(1),pp.407-418,Mar 2020.
  12. B.Bhoi,N.Mishra,L.Jamal,M.Pradhan.Low-cost synthesis approach for reversible authenticator circuits in QCA environment,International Journal of Nanoelectronics and Materials,pp.205-220,2019.
  13. B.Bhoi,N.Mishra,M.Pradhan.Analysis on Fault Mapping of Reversible Gates with Extended Hardware Description Language for Quantum Dot Cellular Apporach,Sensor Letters,17,pp.371-378,2019.
  14. B.Bhoi,N.Mishra,M.Pradhan.Design of magnetic dipole based 3D integration nano-circuits for future electronics application,International Journal of Nano Dimension,9,pp.374-385,2018.
  15. B.Bhoi,N.Mishra,M.Pradhan.A novel vedic divider based crypto hardware for nano computing paradigm,International Journal of Nano Dimension,9,pp.336-345,2018.
  16. R.Barik,B.Bhoi,M.Pradhan.An efficient redundant binary adder with revised computational rules,ElsevierComputers & Electrical Engineering,72,pp.224-236,2018.
  17. B.Bhoi,N.Mishra,M.Pradhan.A Universal Reversible Gate Architecture for Designing N-Bit Comparator Structure in Quantum-dot Cellular Automata,International Journal of Grid Distrbuted Computing,10,pp.33-46,2017.
  18. B.Bhoi,N.Mishra,M.Pradhan.Design and evaluation of an efficient parity-preserving reversible QCA gate with online testability,Taylor & Francis Cogent engineering,4(1),pp.1-18,2017.
  19. R. Barik ,M.Pradhan,R.Panda.Efficient Conversion technique from Redundant Binary to Non redundant Binary representation,Journal of Circuits Systems and Computers, World Scientific Journal,16,pp.1-18,2017, Singapore.
  20. M.Pradhan,R.Panda, FPGA Based design and implementation of ALU. Advances in Modeling,AMSE Journal, Series D, Computer Science and Statistics,15(1),pp.20-29,2010, France.[SCImago journal and country rank value-0.12, H index: 6 ]

National Publications

  1. S.Mishra, M.Pradhan, Implementation of karatsuba algorithm using polynomial multiplication. Indian Journal of Computer Science and Engineering (IJCSE), 3(1), pp.88-93,2012,India.
NIL
DATA TO BE UPDATED...
1. Recent Advancements in Signal Processing,Microwave and VLSI,2018. 2. Skill development program on repairment of cell phones conducted by ETC department,2016.
Former H.O.D (ETC), FormerAssistant Superintendent, Hostel, Former Co-Vice President, Athletic Club,Former Warden, Hall of Residence, FormerVice President, Dramatic Club,Former NSS- Coordinator,FormerVice President, Cultural Association
DATA TO BE UPDATED...
Present Address : 
Department of ETC Engineering VSS University of Technology, Burla Sambalpur-768018,Odisha 		  Permanent Address : 
A.Katapali, PS-Burla,Sambalpur-768006,Odisha